Register Description
4.2
Special Purpose Registers: IOM®-1 Mode
The following register description is only valid if IOM-1 mode is selected (ADF2:IMS = 0).
For IOM-2 mode refer to chapter 4.3.
4.2.1
Serial Port Control Register
SPCR
Read/Write Address 30
H
Value after reset: 00
H
7
0
SPU
SAC
SPM
TLP
C1C1 C1C0 C2C1 C2C0
Important Note After a hardware reset the pins SDAX/SDS1 and SCA/FSD/SDS2 are both
"low" and have the functions of SDS1 and SDS2 in terminal timing mode
(since SPM = 0), respectively, until the SPCR is written to for the first time.
From that moment on, the function taken on by these pins depends on the
state of the IOM Mode Select bit IMS (ADF2 register).
SPU
Software Power Up
Used in TE mode only.
If ADF1:CFS=1, before activating the ISDN S-interface in TE mode the SPU-bit has
to be set to "1" and then cleared again:
After a subsequent CISQ interrupt (C/I code change; ISTA) and reception of the C/I
code "PU" (Power Up indication in TE mode) the reaction of the processor would be:
– to write an Activate Request command as C/I code in the CIXR register.
– to reset the SPU-bit and wait for the following CISQ interrupt.
SAC
SPM
SIP Port Activation
SIP port is in high impedance state (SAC = 0) or operating (SAC = 1).
Serial Port Timing Mode
Depending on the interface mode, the following timing options are provided.
0: Timing mode 0; SIP (SLD) operates in master mode, SCA supplies the 128-kHz
data clock signal for port A (SSI).
typical applications: TE, NT modes
1: Timing mode 1; SIP (SLD) operates in slave mode, FSD supplies a delayed
frame synchronization signal for the IOM interface, serial port A (SSI) is not
used.
typical applications: LT-T, LT-S modes
Semiconductor Group
219
INFINEON [ Infineon ]
