Register Description
Note: If the value FF is programmed in TEI1, received numbered frames with address
H
SAPI1-TEI1 (SAPI1-TEIG) are not handled autonomously by the ISAC-S.
In auto and non-auto-modes with one-byte address field, TEI1 is a command
address, according to X.25 LAPB.
4.1.18 Receive HDLC Control Register
RHCR
Read
Address 29
H
7
0
In all modes except transparent modes 2 and 3, this register contains the control field of a
received HDLC frame. In transparent modes 2 and 3, the register is not used.
Contents of RHCR
Mode
Modulo 8
(MCS = 0)
Modulo 128
(MCS = 1)
Contents of RFIFO
From 3rd byte after flag
Auto-mode,
1-byte address
(U/I frames)
Control field
U-frames only:
Control field
(Note 4)
(Note 2)
(Note 1)
From 4th byte after flag
(Note 4)
Auto-mode,
2-byte address
(U/I frames)
Control field
U-frames only:
Control field
(Note 2)
(Note 1)
From 4th byte after flag
(Note 4)
Auto-mode,
1-byte address
(I frames)
Control field in
compressed form
(Note 3)
From 5th byte after flag
(Note 4)
Auto-mode,
2-byte address
(I frames)
Control field in
compressed form
(Note 3)
2nd byte after flag
3rd byte after flag
3rd byte after flag
From 3rd byte after flag
From 4th byte after flag
Non-auto-mode,
1-byte address
Non-auto-mode,
2-byte address
From 4th byte after flag
From 1st byte after flag
From 2nd byte after flag
Transparent mode 1
Transparent mode 2 –
Transparent mode 3 –
Semiconductor Group
215
INFINEON [ Infineon ]
