Register Description
TLP
Test Loop
When set to 1 the IDP1 and IDP0 lines are internally connected together, and the
times T1 and T2 are reduced (cf. TIMR).
C1C1, C1C0 Channel 1 Connect
Switching of B1 Channel
C1R
B1CR
Read
C1C1
C1C0
Read
Write
Application(s)
0
0
1
1
0
1
0
1
SIP
SIP
SDAR
IOM
SIP
–
–
IOM
IOM
IOM
–
B1 not switched, SIP looping
B1 switched to/from SIP
B1 switched to/from SPa (SSI)
IOM looping
IOM
C2C1, C2C0 Channel 2 Connect
Switching of B2 Channel
C2R
B2CR
Read
C2C1
C2C0
Read
Write
Application(s)
0
0
1
1
0
1
0
1
SIP
SIP
SDAR
IOM
SIP
–
–
IOM
IOM
IOM
–
B2 not switched, SIP looping
B2 switched to/from SIP
B2 switched to/from SPa (SSI)
IOM looping
IOM
4.2.2
Command/Indication Receive RegisterCIRR
Read
Address 31
H
Value after reset: 7C
7
H
0
SQC
BAS
CIC0
0
CODR
SQC
S/Q Channel Change
A change in the received 4-bit S channel (TE or LT-T mode) or Q channel (NT or LT-S
mode) has been detected. The new code can be read from SQRR. This bit is reset
by a read of SQRR.
Semiconductor Group
220
INFINEON [ Infineon ]
