Register Description
VN1-0 Version Number of Chip
PEB 2085
PEB 2086
0 ... A1 to A2 version
1 ... B1 version
0 ... V1.1
2 ... B2 version
3 ... V2.3 (B3) version
OV
Overflow
A "1" in this bit position indicates a message longer than 4095 bytes.
RBC8-11Receive Byte Count
Four most significant bits of the total number of bytes in a received message.
Note:
Normally RBCH and RBCL should be read by the processor after an RME interrupt
in order to determine the number of bytes to be read from the RFIFO, and the total
message length. The contents of the registers are valid only after an RME interrupt,
and remain so until the frame is acknowledged via the RMC bit.
4.1.21 Status Register 2
STAR2
Read/Write Address 2B
H
Value after reset: 00
H
a) WRITE
7
0
0
0
0
0
0
MULT
0
0
MULT Used in NT/LT-S modes to enable or disable the multiframe structure (see
chapter 2.5.1.9)
1: S/T multiframe disabled
0: S/T multiframe enabled
b) READ
7
0
0
0
0
0
WFA MULT TREC SDET
WFA
Waiting for Acknowledge
This bit shows, if the last transmitted I-frame was acknowledged, i.e. V(A) = V(S)
( WFA = 0) or was not yet acknowledged, i.e. V(A) < V(S) ( WFA = 1).
MULT The value written into the register bit is read.
TREC Timer Recovery Status:
0: The device is not in the Timer Recovery state.
1: The device is in the Timer Recovery state.
Semiconductor Group
217
INFINEON [ Infineon ]
