Register Description
Note 1: S frames are handled automatically and are not transferred to the microprocessor.
Note 2: For U frames (bit 0 of RHCR = 1) the control field is as in the modulo 8 case.
Note 3: For I frames (bit 0 of RHCR = 0) the compressed control field has the same format
as in the modulo 8 case, but only the three LSB’s of the receive and transmit counters
are visible:
7
0
N(R)2-0
P
N(S)2-0
0
Note 4: I-field.
4.1.19 TEI2 Register
TEI2
Write
Address 29
H
7
0
EA
TEI2
EA
Address Field Extension Bit
This bit is to be set to "1" according to HDLC/LAPD.
In all message transfer modes except in transparent modes 2 and 3, TEI2 is used by the ISAC-
S for address recognition. In the case of a two-byte address field, it contains the value of the
second programmable Terminal Endpoint Identifier according of the ISDN LAPD protocol.
In auto and non-auto-modes with one-byte address field, TEI2 is a response address,
according to X.25 LAPB.
4.1.20 Receive Frame Byte Count High
RBCH
Read
Address 2A
H
Value after reset: 0XX00000 .
2
7
0
XAC
VN1
VN0
OV
RBC11 RBC10 RBC9 RBC8
XAC
Transmitter Active
The HDLC transmitter is active when XAC = 1. This bit may be polled. The XAC bit is
active when
– either an XTF/XIF command is issued and the frame has not been completely
transmitted
– or the transmission of an S frame is internally initiated and not yet completed.
Semiconductor Group
216
INFINEON [ Infineon ]
