Register Description
MDS2 Mode
MDS1
Number
of
Addresss Comparison
Remark
1. Byte
2. Byte
MDS0
Address
Bytes
Auto-mode
TEI1, TEI2
–
0 0 0
1
One-byte address
compare. HDLC protocol
handling for frames with
address TEI1
Auto-mode
SAP1, SAP2, SAPG
TEI1, TEI2, TEIG
0 0 1
2
Two-byte address
compare. LAPD protocol
handling for frames with
address SAP1 + TEI1
Non-auto-
mode
TEI1, TEI2
–
0 1 0
0 1 1
1
2
One-byte address
compare.
Non-auto-
mode
SAP1, SAP2, SAPG
TEI1, TEI2, TEIG
Two-byte address
compare.
Reserved
1 0 0
1 0 1
Transparent
mode 1
–
TEI1, TEI2, TEIG
>1
–
Low-byte address
compare.
Transparent
mode 2
–
–
–
1 1 0
No address compare.
All frames accepted.
Transparent
mode 3
SAP1, SAP2, SAPG
1 1 1
>1
High-byte address
compare.
Note: SAP1, SAP2: two programmable address values for the first received address byte
(in the case of an address field longer than 1 byte); SAPG = fixed value FC/FE .
H
TEI1, TEI2: two programmable address values for the second (or the only, in the case
of a one-byte address) received address byte; TEIG = fixed value FF .
H
TMD
Timer Mode
Sets the operating mode of the ISAC-S timer. In the external mode (0) the timer is
controlled by the processor. It is started by setting the STI bit in CMDR and it is
stopped by a write of the TIMR register.
In the internal mode (1) the timer is used internally by ISAC-S for timeout and retry
conditions (handling of LAPD/HDLC protocol in auto-mode).
Semiconductor Group
205
INFINEON [ Infineon ]
