Register Description
RAC
Receiver Active
The HDLC receiver is activated when this bit is set to "1".
DIM2-0 Digital Interface Mode
These bits define the characteristics of the IOM Data Ports (IDP0, IDP1) according to
following tables:
IOM®-1 Modes (ADF2:IMS = 0)
DIM2-0
000
×
Characteristics
IOM frame structure
HDLC interface
001
010
011
100
101-111
×
×
×
×
×
×
×
×
×
×
×
×
MONITOR channel used for
TIC bus access 1)
MONITOR channel used for
data transfer 2)
MONITOR channel Stop/Go
bit evaluated for D-channel
access handling
×
Reserved
Applications
TE mode
(×)1
(×)1
×
×
LT-T mode with D-channel
collision resolution
×
LT-T, NT, LT-S modes
with transparent D channel
×
Test purposes
1)
Notes:
If the TIC bus access handling is not required, i.e. if only one layer-2 device
occupies the D and C/I channel, the TIC bus address should be programmed to
"111" e.g. STCR = 70 .
H
2)
This function is only meaningful in test mode (ADF1:TEM = 1) for data transfers
with external layer-1 devices (IBC PEB 2095, IEC PEB 2091).
Semiconductor Group
206
INFINEON [ Infineon ]
