Register Description
XPR
Transmit Pool Ready
A data block of up to 32 bytes can be written to the XFIFO.
An XPR interrupt will be generated in the following cases:
– after an XTF or XIF command, when one transmit pool is emptied and the frame is
not yet complete
– after an XTF together with an XME command is issued, when the whole
transparent frame has been transmitted
– after an XIF together with an XME command is issued, when the whole I-frame has
been transmitted and a positive acknowledgement from the remote station has
been received, (auto-mode).
TIN
Timer Interrupt
The internal timer and repeat counter has expired (see TIMR register).
CISQ
C/I or S/Q Channel Change
A change in C/I channel 0, C/I channel 1 (only in IOM-2 TE mode) or S/Q channel has
been recognized. The actual value can be read from CIR0, CIR1 or SQRR.
SIN
EXI
Synchronous Transfer Interrupt
When programmed (STCR register), this interrupt is generated to enable the
processor to lock on to the IOM timing, for synchronous transfers.
Extended Interrupt
This bit indicates that one of six non-critical interrupts has been generated. The exact
interrupt cause can be read from EXIR.
Note: A read of the ISTA register clears all bits except EXI and CISQ. EXI is cleared by
reading the EXIR register, CISQ is cleared by reading CIRR/CIR0.
4.1.4
Mask Register
MASK
Write
Address 20
H
Value after reset: 00
7
H
0
RME
RPF
RSC
XPR
TIN
CISQ
SIN
EXI
Each interrupt source in the ISTA register can be selectively masked by setting to "1"
the corresponding bit in MASK. Masked interrupt status bits are not indicated when
ISTA is read. Instead, they remain internally stored and pending, until the mask bit is
reset to zero.
Note: In the event of an extended interrupt and of a C/I or S/Q channel change, EXI and
CISQ are set in ISTA even if the corresponding mask bits in MASK are active, but no
interrupt (INT pin) is generated.
4.1.5
Status Register
STAR
Read
Address 21
H
Semiconductor Group
201
INFINEON [ Infineon ]
