Register Description
4.1.6
Command Register
CMDR
Write
Address 21
H
Value after reset: 00
7
H
0
RMC RRES RNR
STI
XTF
XIF
XME XRES
Note: The maximum time between writing to the CMDR register and the execution of the
command is 2.5 DCL clock cycles. During this time no further commands should be
written to the CMDR register to avoid any loss of commands.
RMC
Receive Message Complete
Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By
setting this bit, the processor confirms that it has fetched the data, and indicates that
the corresponding space in the RFIFO may be released.
RRES Receiver Reset
HDLC receiver is reset, the RFIFO is cleared of any data.
In addition, in auto-mode, the transmit and receive counters (V(S), V(R)) are reset
RNR
Receiver Not Ready
Used in auto-mode only.
Determines the state of the ISAC-S HDLC receiver.
When RNR = "0", a received I or S-frame is acknowledged by an RR supervisory
frame, otherwise by an RNR supervisory frame.
STI
XTF
XIF
Start Timer
The ISAC-S hardware timer is started when STI is set to one. In the internal timer
mode (TMD bit, MODE register) an S-Command (RR, RNR) with poll bit set is
transmitted in addition. The timer may be stopped by a write of the TIMR register.
Transmit Transparent Frame
After having written up to 32 bytes in the XFIFO, the processor initiates the
transmission of a transparent frame by setting this bit to "1". The opening flag is
automatically added to the message by the ISAC-S.
Transmit I-Frame
Used in auto-mode only
After having written up to 32 bytes in the XFIFO, the processor initiates the
transmission of an I-frame by setting this bit to "1". The opening flag, the address and
the control field are automatically added by the ISAC-S.
Semiconductor Group
203
INFINEON [ Infineon ]
