Register Description
XME
Transmit Message End
By setting this bit to "1" the processor indicates that the data block written last in the
XFIFO completes the corresponding frame. The ISAC-S terminates the transmission
by appending the CRC and the closing flag sequence to the data.
XRES Transmitter Reset
HDLC transmitter is reset and the XFIFO is cleared of any data.
This command can be used by the processor to abort a frame currently in
transmission.
Notes: ● After an XPR interrupt further data has to be written in the XFIFO and the
appropriate Transmit Command (XTF or XIF) has to be written in the CMDR
register again to continue transmission, when the current frame is not yet complete
(see also XPR in ISTA).
● During frame transmission, the 0-bit insertion according to the HDLC bit-stuffing
mechanism is done automatically.
4.1.7
Mode Register
MODE
Read/Write Address 22
H
Value after reset: 00
7
H
0
MDS2 MDS1 MDS0 TMD
RAC
DIM2 DIM1 DIM0
MDS2-0 Mode Select
Determines the message transfer mode of the HDLC controller, as follows:
Semiconductor Group
204
INFINEON [ Infineon ]
