Register Description
The internal timer procedure will be started in auto-mode:
– after start of an I-frame transmission
or
– after an "RNR" S-frame has been received.
After the last retry, a timer interrupt (TIN-bit in ISTA) is generated.
The timer procedure will be stopped when
– a TIN interrupt is generated. The time between the start of an I-frame
transmission or reception of an "RNR" S-frame and the generation of a TIN
interrupt is equal to: (CNT+1) × T1.
– or the TIMR is written
– or a positive or negative acknowledgement has been received.
Note: The maximum value of CNT can be 6. If CNT is set to 7, the number of retries
is unlimited.
* External Timer Mode (TMD = 0)
CNT together with VALUE determine the time period T2 after which a TIN interrupt
will be generated:
CNT × 2.048 s + T1
with T1 = (VALUE + 1) × 0.064 s,
in the normal case, and
T2 = 16348 × CNT × DCL + T1
with T1 = 512 × (VALUE + 1) × DCL
when TLP = 1 (test loop activated, SPCR register).
DCL denotes the period of the DCL clock.
The timer can be started by setting the STI-bit in CMDR and will be stopped when a
TIN interrupt is generated or the TIMR register is written.
Note: If CNT is set to 7, a TIN interrupt is indefinitely generated after every
expiration of T1.
VALUE Determines the Time Period T1:
T1 = (VALUE + 1) × 0.064 s (SPCR:TLP = 0, normal mode)
T1 = 512 × (VALUE + 1) × DCL (SPCR:TLP = 1, test mode).
Semiconductor Group
208
INFINEON [ Infineon ]
