Register Description
4.1
HDLC Operation and Status Registers
Receive FIFO RFIFO
4.1.1
Read
Address 00-1F
H
A read access to any address within the range 00-1F gives access to the "current" FIFO
H
location selected by an internal pointer which is automatically incremented after each read
access. This allows for the use of efficient ’move string’ type commands by the processor.
The RFIFO contains up to 32 bytes of received frame.
After an ISTA:RPF interrupt, exactly 32 bytes are available.
After an ISTA:RME interrupt, the number of bytes available can be obtained by reading the
RBCL register.
4.1.2
Transmit FIFO
XFIFO
Write
Address 00-1F
H
A write access to any address within the range 00-1F gives access to the "current" FIFO
H
location selected by an internal pointer which is automatically incremented after each write
access. This allows for the use of efficient ’move string’ type commands by the processor.
Up to 32 bytes of transmit data can be written into the XFIFO following an ISTA:XPR interrupt.
4.1.3
Interrupt Status Register
ISTA
Read
Address 20
H
Value after reset: 00
H
7
0
RME
RPF
RSC
XPR
TIN
CISQ
SIN
EXI
RME
Receive Message End
One complete frame of length less than or equal to 32 bytes, or the last part of a frame
of length greater than 32 bytes has been received. The contents are available in the
RFIFO. The message length and additional information may be obtained from
RBCH + RBCL and the RSTA register.
RPF
RSC
Receive Pool Full
A 32-byte block of a frame longer than 32 bytes has been received and is available
in the RFIFO. The frame is not yet complete.
Receive Status Change. Used in auto-mode only.
A status change in the receiver of the remote station – Receiver Ready/Receiver Not
Ready – has been detected (RR or RNR S-frame).
The actual status of the remote station can be read from the STAR register (RRNR
bit).
Semiconductor Group
200
INFINEON [ Infineon ]
