Operational Description
MOS interrupt logic
The MOS interrupt logic shown in figure 68 is valid only in the case of IOM-2 interface mode.
Further, only one MONITOR channel is handled in the case of IOM-2 non-terminal timing mo-
des. In this case, MOR1 and MOX1 are unused.
The MONITOR Data Receive (MDR) and the MONITOR End of Reception (MER) interrupt
status bits have two enable bits, MONITOR Receive interrupt Enable (MRE) and MR bit
Control (MRC). The MONITOR channel Data Acknowledged (MDA) and MONITOR channel
Data Abort (MAB) interrupt status bits have a common enable bit MONITOR Interrupt Enable
(MXE).
MRE prevents the occurrence of the MDR status, including when the first byte of a packet is
received. When MRE is active (1) but MRC is inactive, the MDR interrupt status is generated
only for the first byte of a receive packet. When both MRE and MRC are active, MDR is gene-
rated and all received monitor bytes – marked by a 1-to-0 transition in MX bit – are stored. (Ad-
ditionally, an active MRC enables the control of the MR handshake bit according to the MONI-
TOR channel protocol.)
In IOM-1 mode the reception of a monitor byte is immediately indicated by the MOS interrupt
status, and registers MOCR and MOSR are not used.
Control of edge-triggered interrupt controllers
The INT output is level active. It stays active until all interrupt sources have been serviced. If
a new status bit is set while an interrupt is serviced, the INT line stays active. This may cause
problems if the ISAC-S is connected to edge-triggered interrupt controllers (figure 69).
To avoid these problems, it is recommended to mask all interrupts at the end of the interrupt
service program and to enable the interrupts again. This is done by writing FF to the MASK
H
register and to write back the old value of the MASK register (figure 70).
Semiconductor Group
164
INFINEON [ Infineon ]
