Operational Description
3.2
Interrupt Structure and Logic
Since the ISAC-S provides only one interrupt request output (INT), the cause of an interrupt is
determined by the microprocessor by reading the Interrupt Status Register ISTA. In this
register, seven interrupt sources can be directly read. The LSB of ISTA points to eight non-
critical interrupt sources which are indicated in the Extended Interrupt Register EXIR
(figure 68).
INT
RME
RPF
RSC
XPR
TIN
RME
RPF
RSC
XPR
TIN
CISQ
SIN
CISQ
SIN
EXI
EXI
MASK
ISTA
SQIE
SQC
BAS
C
O
D
R
0
XMR
XDU
PCE
RFO
SOV
MOS
SAW
WOV
SQRR
CIR1
CIC0
CIC1
CI1E
EXIR
SQXR
CIR0
MDR1
MER1
MDA1
MAB1
MDR0
MER0
MDA0
MAB0
MRE1
MXE1
MRE0
MXE0
IOM R -2 only
ITD02578
MOCR
MOSR
Figure 68
ISAC®-S Interrupt Structure
Semiconductor Group
162
INFINEON [ Infineon ]
