Operational Description
The microprocessor interface signals are summarized in table 11.
Table 11
µP Interface of the ISAC®-S
Pin No. Pin No.
Pin No.
Function
Input (I)
Symbol
P-DIP-40 P-LCC-44
Output (O)
Open Drain
(OD)
P-MQFP-64
37
38
39
40
1
2
3
4
41
42
43
44
1
2
3
4
Multiplexed Bus Mode: Address/Data
bus. Transfers addresses from the µP
system to the ISAC-S and data between
the µP system and the ISAC-S.
Non-Multiplexed Bus Mode: Data bus.
Transfers data between the µP system and
the ISAC-S.
37
38
39
40
41
42
43
44
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AD0/D0
AD1/D1
AD2/D2
AD3/D3
AD4/D4
AD5/D5
AD6/D6
AD7/D7
34
37
Chip Select. A 0 ("low") on this line selects
the ISAC-S for a read/write operation.
27
28
I
I
CS
38
Read/Write. A 1 ("high"), identifies a valid
µP access as a read operation. A 0,
identifies a valid µP access as a write
operation (Motorola bus mode).
R/W
I
I
35
38
39
Write. This signal indicates a write
operation (Siemens/Intel bus mode).
28
29
WR
DS
Data Strobe. The rising edge marks the
end of a valid read or write operation
(Motorola bus mode).
36
20
39
23
Read. This signal indicates
operation (Siemens/Intel bus mode).
a
read
29
8
RD
I
OD
Interrupt Request. The signal is activated
when the ISAC-S requests an interrupt. It is
an open drain output.
INT
33
36
Address Latch Enable. A high on this line
indicates an address on the external
address bus (Multiplexed bus type only).
ALE also selects the µP interface type
(multiplexed or non-multiplexed).
26
ALE
I
40
6
Address Bit 0 (Non-multiplexed bus type).
Address Bit 1 (Non-multiplexed bus type).
Address Bit 2 (Non-multiplexed bus type).
Address Bit 3 (Non-multiplexed bus type).
Address Bit 4 (Non-multiplexed bus type).
Address Bit 5 (Non-multiplexed bus type).
30
51
A0
A1
A2
I
I
I
I
I
I
5
50
64
63
18
17
10
A3
A4
55
A5
Semiconductor Group
161
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