Operational Description
DCL
INT
RD
ITD02388
Figure 71
Timing of INT Pin
The INT line is switched with the rising edge of DCL. If no pending interrupts are internally
stored, a reading of ISTA respectively EXIR or CIR0 switches the INT line to high as indicated
in figure 71.
3.3
Control of Layer 1
3.3.1
Activation/Deactivation of IOM® Interface
In LT-T and LT-S applications the IOM interface should be kept active, i.e. the clock DCL and
the frame sync FSC1/2 (inputs) should always be supplied by the system.
In TE and NT applications the IOM interface can be switched off in the inactive state,
reducing power consumption to a minimum. In this deactivated state the clock line is low and
the data lines are high.
In TE mode the IOM interface can be kept active while the S interface is deactivated by setting
the CFS bit to "0" (ADF1 register in IOM-1, SQXR register in IOM-2 mode). This is the case
after a hardware reset. If the IOM interface should be switched off while the S interface is
deactivated, the CFS bit should be set to "1". In this case the internal oscillator is disabled
when no signal (info 0) is present on the S bus. If the TE wants to activate the line, it has first
to activate the IOM interface either by using the "Software Power Up" function (SPCR:SPU bit)
or by setting the CFS bit to "0" again.
For the TE case the deactivation procedure is shown in figure 72. After detecting the code DIU
(Deactivate Indication Upstream, i.e. from TE to NT/LT-S) the layer 1 of the ISAC-S responds
by transmitting DID (Deactivate Indication Downstream) during subsequent frames and stops
the timing signals synchronously with the end of the last C/I (C/I0) channel bit of the fourth
frame.
Semiconductor Group
166
INFINEON [ Infineon ]
