Operational Description
➀
➂
INT
➄
➁
➃
➀ A status bit is set. This causes an interrupt.
➁ The microprocessor starts its service routine and reads the status registers.
➂ A new status bit is set before the first status bit has been read.
➃ The first status bit is read.
➄ The INT output stays active but the interrupt controller will not serve the interrupt
(edge triggered).
Figure 69
INT Handling
➀
➂
INT
➁
➃
➄ ➅
➆
➇
➈
➀ to ➃ see above
➄ ’FF’ is written to the MASK register. This masks all interrupts and returns the INT
output to its inactive state.
➅ The old value is written to the MASK register. This will activate the INT output if
an interrupt source is still active.
➆ The microprocessor starts a new interrupt service program.
➇ The last status bit is read.
➈ The INT output is inactive.
Figure 70
Service Program for Edge-Triggered Interrupt Controllers
Semiconductor Group
165
INFINEON [ Infineon ]
