Operational Description
3.1
Microprocessor Interface Operation
The ISAC-S is programmed via an 8-bit parallel microcontroller interface. Easy and fast
microprocessor access is provided by 8-bit address decoding on the chip. Depending on the
chip package (P-DIP-40, P-LCC-44 or M-QFP-64) either one or three types of µP buses are
provided:
P-DIP-40 package:
The ISAC-S microcontroller interface is of the Siemens/Intel multiplexed address/data bus
type with control signals CS, WR, RD, ALE.
P-LCC-44/P-MQFP-64 package:
The ISAC-S microcontroller interface can be selected to be either of the
(1) – Motorola type with control signals CS, R/W, DS
(2) – Siemens/Intel non-multiplexed bus type with control signals CS, WR, RD
(3) – or of the Siemens/Intel multiplexed address/data bus type with control
signals CS, WR, RD, ALE.
The selection is performed via pin ALE as follows:
ALE tied to VDD
ALE tied to VSS
Edge on ALE
(1)
(2)
(3).
The occurrence of an edge on ALE, either positive or negative, at any time during the operation
immediately selects interface type (3). A return to one of the other interface types is possible
only if a hardware reset is issued.
Notes: 1) If the multiplexed address/data bus type (3) is selected, the unused address pins
A0-A5 are internally not evaluated and may thus be left open. It is however
recommended to tie the unused input pins to a defined voltage level (e.g. VSS or
VDD).
2) If the non-multiplexed bus types (1) or (2) are selected, the serial interfaces SLD
and SSI can no longer be used since pin 5 (SDAR)/A2 and pin 10 (SIP/EAW)/A5
now have the function of address pins. These µP bus types are therefore primarily
intended to be used in IOM-2 modes (ADF2:IMS=1).
If however the PEB 2086 P-MQFP-64 package is used, the demultiplexed micro-
processor interface is also available in IOM-1 mode.
Semiconductor Group
160
INFINEON [ Infineon ]
