Operational Description
The clock pulses will be enabled again when the IDP1 line is pulled low (bit SPU, SPCR
register) i.e. the C/I command TIM = "0000" is received by layer 1, or when a non-zero level
on the S-line interface is detected. The clocks are turned on after approximately 0.2 to 4 ms
depending on the capacitances on XTAL 1/2.
DCL is activated such that its first rising edge occurs with the beginning of the bit following the
C/I (C/I0) channel.
After the clocks have been enabled this is indicated by the PU code in the C/I channel and,
consequently, by a CISQ interrupt. The IDP1 line may be released by resetting the Software
Power Up bit SPCR:SPU=0, and the C/I code written in CIX0 is output on IDP1.
(a) IOM®–1
CISQ Int.
SPU = 1
SPU = 0
(AR)
IDP1
IDP0
PU
PU
PU
0.2 to 4 ms
FSC1/2
DCL
ITD02389
4 x DCL
Figure 73
Activation of the IOM® Interface (CFS=1, Register ADF1 (IOM®-1)/SQXR (IOM®-2))
Semiconductor Group
168
INFINEON [ Infineon ]
