AN985B/BX
Registers and Descriptors Description
RDES1
RDES1
RDES1
Offset
04H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
5(5&
5HV
UR
5HV
5%6ꢀ
5%6ꢁ
5 +
UZ UZ UR
UZ
UZ
Field
Res
RER
Bits
31:26
25
Type
ro
rw
Description
Reserved
Receive End of Ring
Indicates this descriptor is last, return to base address of descriptor.
RCH
24
rw
Second Address Chain
Use for chain structure. Indicates the buffer2 address is the next
descriptor address.Ring mode takes precedence over chained mode
Res
RBS2
23:22
21:11
ro
rw
Reserved
Buffer 2 Size
DW boundary
RBS1
10:0
rw
Buffer 1 Size
DW boundary
RDES2
RDES2
RDES2
Offset
08H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
5%$ꢀ
UZ
Field
Bits
Type
Description
RBA1
31:0
rw
Receive Buffer Address 1
This buffer address should be double word aligned.
RDES3
Data Sheet
97
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
