AN985B/BX
Registers and Descriptors Description
8.4
Descriptors and Buffer Management
Table 17
Registers Overview
Register Short Name
RDES0
Register Long Name
RDES0
Offset Address Page Number
00H
94
RDES1
RDES1
04H
97
RDES2
RDES2
08H
97
RDES3
TDES0
RDES3
TDES0
0ChH
00H
97
98
TDES1
TDES1
04H
99
TDES2
TDES3
TDES2
TDES3
08H
0ChH
100
100
The register is addressed wordwise.
Standard abbreviations:
Table 18
Mode
Registers Access Types
Symbol Description Hardware (HW)
Description Software (SW)
read/write
rw
Register is used as input for the HW
Register is read and writable by SW
read
r
Register is written by HW (register
Value written by software is ignored by
between input and output -> one cycle hardware; that is, software may write any
delay)
value to this field without affecting hardware
behavior (= Target for development.)
write
w
Register is writable by SW
read/write
hardware
affected
rwh
Register can be modified by HW
Register can be modified by HW, but the
priority SW versus HW has to be specified
rwv
ro
Read only
Register is set by HW (register between SW can only read this register
input and output -> one cycle delay)
Read virtual
rv
Physically, there is no new register, the SW can only read this register
input of the signal is connected directly
to the address multiplexer.
Latch high,
self clearing
Latch low,
self clearing
lhsc
llsc
Latch high signal at high level, clear on SW can read the register
read
Latch high signal at low-level, clear on SW can read the register
read
Latch high,
lhmk
llmk
Latch high signal at high level, register SW can read the register, with write mask
mask clearing
cleared with written mask
the register can be cleared (1 clears)
Latch low,
mask clearing
Latch high signal at low-level, register SW can read the register, with write mask
cleared on read the register can be cleared (1 clears)
Data Sheet
93
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
