AN985B/BX
Registers and Descriptors Description
RDES3
RDES3
Offset
0ChH
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
5%$ꢀ
UZ
Field
Bits
Type
Description
RBA2
31:0
rw
Receive Buffer Address 2
This buffer address should be double word aligned.
8.4.2
Transmit Descriptor Descriptions
The AN985B/BX provides receive and transmit descriptors for packet buffering and management.
Descriptor addresses must be longword alignment
Table 20
Transmit Descriptor Table
31 ----------------------------------------------------------------------------------------------------------------------------- 0
TDES0
TDES1
TDES2
TDES3
Own
Control
Buffer1 address
Buffer2 address
Status
Buffer2 byte-count
Buffer1 byte-count
TDES0
TDES0
TDES0
Offset
00H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢃ
ꢁ ꢂ
2:
5H
V
5HV
UR
85
5HV
UR
(6 72 5HV /21& /& (& +)
&&
UZ
8) '(
1
UZ
UZ
UZ UZ UR UZ UZ UZ UZ UZ
UR UZ UZ
Field
OWN
Bits
31
Type
rw
Description
Own Bit
0B
1B
, No transmit data in this descriptor for transmission
, Indicate this descriptor is ready to transmit
Res
UR
Res
30:24
23:22
21:16
ro
rw
ro
Reserved
Under-run Count
Reserved
Data Sheet
98
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
