AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
ES
15
rw
Error Summary, OR of the Following Bit
1: under-run error
8: excessive collision
9: late collision
10: no carrier
11: loss carrier
14: jabber time-out
TO
Res
LO
NC
LC
EC
HF
CC
Res
UF
DE
14
13:12
11
10
9
8
7
6:3
2
1
rw
ro
Transmit Jabber Time-out
Reserved
Loss Carrier
rw
rw
rw
rw
rw
rw
ro
No Carrier
Late Collision
Excessive Collision
Heartbeat Fail
Collision Count
Reserved
rw
rw
Under-run Error
Deferred
0
TDES1
TDES1
TDES1
Offset
04H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ ꢀ ꢃ ꢁ ꢂ
7( 7& '3 5H
,& /6 )6 5HV $&
7%6ꢀ
7%6ꢁ
UZ
5 + '
V
UZ UZ UZ UR UZ UZ UZ UZ UR
UZ
Field
IC
LS
FS
Res
AC
Bits
31
30
29
28:27
26
Type
rw
rw
rw
ro
rw
rw
rw
Description
Interrupt Completed
Last Descriptor
First Descriptor
Reserved
Disable add CRC Function
End of Ring
TER
TCH
25
24
2nd Address Chain
Indicate the buffer2 address is the next descriptor address
DPD
Res
23
22
rw
ro
Disable Padding Function
Reserved
TBS2
TBS1
21:11
10:0
rw
rw
Buffer 2 Size
Buffer 1 Size
Data Sheet
99
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
