AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
TS
22:20
ro
Transmit State
Report the current transmission state only, no interrupt will be generated.
000B , stop
001B , read descriptor
010B , transmitting
011B , FIFO fill read the data from memory and put into FIFO
100B , reserved
101B , reserved
110B , suspended, unavailable transmit descriptor or FIFO overflow
111B , write descriptor
RS
19:17
ro
Receive State
Report current receive state only, no interrupt will be generated.
000B , stop
001B , read descriptor
010B , check this packet and pre-fetch next descriptor
011B , wait for receiving data
100B , suspended
101B , write descriptor
110B , flush the current FIFO
111B , FIFO drain. move data from receiving FIFO into memory
NISS
AISS
16
15
ro/lh
ro/lh
Normal Interrupt Status Summary
It’s set if any of below bits of CSR5 asserted. (Combines with bit 16 of
ACSR5)
bit0, transmit completed interrupt
bit2, transmit descriptor unavailable
bit6, receive descriptor interrupt
Note: LH = High Latching and cleared by writing 1
Abnormal Interrupt Status Summary
It’s set if any of below bits of CSR5 asserted. (Combines with bit 15 of
ACSR5)
bit1, transmit process stopped
bit3, transmit jabber timer time-out
bit5, transmit under-flow
bit7, receive descriptor unavailable
bit8, receive processor stopped
bit9, receive watchdog time-out
bit11, general purpose timer time-out
bit13, fatal bus error
Note:LH = High Latching and cleared by writing 1
Reserved
Fatal Bus Error
Res
FBE
14
13
ro
ro/lh
Note:LH = High Latching and cleared by writing 1
1B
, while any of parity error master abort, or target abort is occurred
(see bits 25~23 of CSR5). AN985B/BX will disable all bus access.
The way to recover parity error is by setting software reset.
Res
12
ro
Reserved
Data Sheet
54
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
