AN985B/BX
Registers and Descriptors Description
Transmit Descriptor Base Address
TDB_CSR4
Transmit Descriptor Base Address
Offset
20H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
6$7
7%1'
UZꢊ
UR
Field
Bits
Type
Description
SAT
31:2
rw*
Start Address of Transmit Descriptor
Note:rw*: Before writing the trasmitting process should be stopped.
TBND
1:0
ro
Must be 00, DW Boundary
Status Register
SR_CSR5
Status Register
Offset
28H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
1, $, 5H )% 5H *3 5H5:535'5& 78 5H 7- 7' 73 7&
66 66 V V 77 V 6 8 8 6
5HV
UR
%(7
76
56
(
7
,
)
V
7
,
UR
UR
UR
URꢊOKURꢊOKURURꢊOKURURꢊOKURURꢊOKURꢊOKURꢊOKURꢊOKURꢊOKURURꢊOKURꢊOKURꢊOKURꢊOK
Field
Res
Bits
31:26
Type
ro
Description
Reserved
BET
25:23
ro
Bus Error Type
This field is valid only when bit 13 of CSR5 (fatal bus error) is set. There
is no interrupt generated by this field.
000B , parity error
001B , master abort
010B , target abort
011B , reserved
1xxB , reserved
Data Sheet
53
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
