AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
TAP
18:17
rw*
Transmit Auto-polling in Transmit Suspended State
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
00B , disable auto-polling (default)
01B , polling own-bit every 200 μ s
10B , polling own-bit every 800 μ s
11B , polling own-bit every 1600 μ s
Res
CAL
16
15:14
ro
rw*
Reserved
Cache Alignment, Address Boundary for Data Burst, Set after Reset
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
00B , reserved (default)
01B , 8 DW boundary alignment
10B , 16 DW boundary alignment
11B , 32 DW boundary alignment
PBL
BLE
13:8
7
rw*
rw*
Programmable Burst Length
This value defines the maximum number of DW to be transferred in one
DMA transaction. Value: 0 (unlimited), 1, 2, 4, 8, 16 (default), 32
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
Big or Little Endian Selection
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
0B
1B
, little endian (e.g. INTEL)
, big endian (only for data buffer)
DSL
BAR
6:2
1
rw*
rw*
Descriptor Skip Length
Defines the gap between two descriptions in the units of DW.
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
Bus Arbitration
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
0B
1B
, receive higher priority
, transmit higher priority
SWR
0
rw*
Software Reset
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
1B
, reset all internal hardware except configuration registers. This
signal will be cleared by AN985B/BX itself after it completed the
reset process.
Transmit Demand Register
Data Sheet
50
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
