AN985B/BX
Registers and Descriptors Description
Receive Demand Register
RDR_CSR2
Receive Demand Register
Offset
10H
Reset Value
FFFF FFFFH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
53'0
UZꢊ
Field
Bits
Type
Description
RPDM
31:0
rw*
Receive Poll Demand
When written any value in suspended state, trigger the read-rx-descriptor
process and check own-bit, if own- bit = 1, then start move data to buffer
from FIFO.
Note:rw*: Before writing the receiving process should be in the
suspended state.
Receive Descriptor Base Address
RDB_CSR3
Receive Descriptor Base Address
Offset
18H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
6$5
5%1'
UZꢊ
UR
Field
Bits
Type
Description
SAR
31:2
rw*
Start Address of Receive Descriptor
Note:rw*: Before writing the receiving process should be stopped.
RBND
1:0
ro
Must be 00, DW Boundary
Data Sheet
52
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
