AN985B/BX
Registers and Descriptors Description
Power Management Register 1
PMR1_CR49
Power Management Register 1
Offset
C4H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
30 '6&$
30
((
5HV
UR
'6(/
5HV
UR
3:56
(6
/
UZꢊ UR
UZ
UZ
UZ
Field
Res
PMES
Bits
31:16
15
Type
ro
rw*
Description
Reserved
PME Status
This bit is set when the AN985B/BX would normally assert the
PME#/CSTSCHG signal for wake-up event, this bit is independent of the
state of the PME-En bit. Writing a “1” to this bit will clear it and cause the
AN985B/BX to stop asserting a PME#/CSTSCHG (if enabled). Writing a
“0” has no effect.
Note:rw*: Read and Write Clear
DSCAL
DSEL
14:13
12:9
8
ro
Data Scale
Indicates the scaling factor to be used when interpreting the value of the
Data register.
rw
rw
Data Select
This four-bit field is used to select which data is to be reported through the
Data register and Data_Scale field.
PMEE
PME En
“1” enables the AN985B/BX to assert PME#/CSTSCHG. When “0”
disables the PME#/CSTSCHG assertion.
Magic packet default enable:
Csr18 <18> and csr18 <19> are set ->csr13 <9> is set, then #pme
asserts without impact of PME_En.
Res
PWRS
7:2
1:0
ro
rw
Reserved
Power State
This two-bit field is used both to determine the current power state of the
AN985B/BX and to set the AN985B/BX into a new power state. The
definition of this field is given below.
Note:This field is auto cleared to D0 when power resumed.
00B D0,
01B D1,
10B D2,
11B D3hot,
Data Sheet
46
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
