AN985B/BX
Registers and Descriptors Description
8.2
PCI /CARDBUS Control/Status Registers
Table 11
Registers Address Space
Module
Base Address
End Address
Note
PCI/CARDBUS
0000 0000H
0000 010CH
Table 12
Registers Overview
Register Short Name
PAR_CSR0
TDR_CSR1
RDR_CSR2
RDB_CSR3
TDB_CSR4
SR_CSR5
NAR_CSR6
IER_CSR7
LPC_CSR8
SPR_CSR9
TMR_CSR11
WCSR_CSR13
WTMR_CSR15
ACSR5_CSR16
ACSR7_CSR17
CR_CSR18
CARDBUSC_CSR19
PMCSR_CSR20
WTDP_CSR21
WRDP_CSR22
TXBR_CSR23
FROM_CSR24
PAR0_CSR25
PAR1_CSR26
MAR0_CSR27
MAR1_CSR28
UAR0_CSR_29
UAR1_CSR_30
OMR
Register Long Name
Offset Address Page Number
CARDBUS Access Register
Transmit Demand Register
Receive Demand Register
Receive Descriptor Base Address
Transmit Descriptor Base Address
Status Register
Network Access Register
Interrupt Enable Register
Lost Packet Counter
Serial Port Register
General-Purpose Timer
Wake-up Control/Status Register
Watchdog Timer
Assistant CSR5 (Status Register 2)
Assistant CSR7 (Interrupt Enable Register 2)
Command Register
CARDBUS Bus Performance Counter
Power Management Command and Status
Current Working Transmit Descriptor Pointer
Current Working Receive Descriptor Pointer
Transmit Burst Count/Time-out
Flash ROM (also the boot ROM) Port
Physical Address Register 0
Physical Address Register 1
Multicast Address Register 0
Multicast Address Register 1
Unicast Address Register 0
Unicast Address Register 1
Operation Mode Register
00H
08H
10H
18H
20H
28H
30H
38H
40H
48H
58H
68H
78H
80H
84H
88H
8CH
90H
94H
98H
9CH
A0H
A4H
A8H
ACH
B0H
B4H
B8H
FCH
100H
104H
108H
10CH
49
50
52
52
53
53
57
58
61
61
62
62
65
66
67
67
70
70
72
72
73
73
74
74
75
76
77
77
77
78
79
80
80
FER
FEMR
FPSR
FFER
Function Event Register
Function Event Mask Register
Function Present State Register
Function Force Event Register
Data Sheet
47
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
