AN985B/BX
Functional Descriptions
7.5
LED Display Operation
The AN985B/BX provides two LED schemes one is three-LED which provides display pins for Link test
status/Activity status, Speed mode, and Full duplex/Collision status. These pins can directly drive the LED device;
the other is four-LED schemes which provide link100, link10, act, fd/col. The detail descriptions about the
operation are described in the Pin Description section.
7.6
Reset Operation
7.6.1
Reset Whole Chip
There are two ways to reset the AN985B/BX. First, hardware reset, the AN985B/BX can be reset via RST# pin.
For ensuring proper reset operation, at least 100us active Reset input signal is required. Second, software reset,
when bit 0 of CSR0 register is set to 1, the AN985B/BX will reset entire circuits and registers to default values then
clear the bit 0 of CSR0 to 0.
7.6.2
Reset Transceiver Only
When bit 15 of XR0 register is set to 1, the transceiver will reset entire circuits and register contents to default value
then clear the bit 15 of XR0 to 0.
7.7
Wake on LAN Function
The AN985B/BX can assert a signal to wake up the system when it receives a Magic Packet from the network.
The Wake on LAN operation is described as follows:
7.7.1
The Magic Packet Format
•
•
Valid destination address that can pass the address filter of the AN985B/BX
The payload of frame must include at least 6 contiguous ‘FF’ followed immediately by 16 repetitions of IEEE
address
•
•
The frame can contain multiple ‘six FF + sixteen IEEE address’ patterns
CRC OK
7.7.2
The Wake on LAN Operation
The Wake on LAN enable function is controlled by bit 18 of CSR18; it is loaded from the EEPROM after reset or
programmed by a driver to enable Wake on LAN function. If the bit 18 of CSR18 is set and the AN985B/BX
receives a Magic Packet, it will assert the PME# signal (drive to low) to indicated is receiving a wake up frame as
well as to set the PME status bit (the bit 15 of CSR20).
7.8
ACPI Power Management Function
The AN985B/BX has a built-in capability for Power Management (PM), which controlled by the host system
The AN985B/BX will provide:
•
•
•
•
•
Compatibility with Device Class Power Management Reference Specification, Rev1.09
Compatibility with ACPI specification, Rev 1.0
Compatibility with CARDBUS Bus Power Management Interface Specification, Rev 1.1
Compatibility with AMD Magic Packet™ Technology.
Compatibility with CARDBUS CLKRUN scheme.
Data Sheet
31
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
