IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JTAGTIMINGSPECIFICATION
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
5994 drw11
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t5
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 6. Standard JTAG Timing
JTAG
ACELECTRICALCHARACTERISTICS
(vcc = 2.5V ± 5%; Tcase = 0°C to +85°C)
Parameter
Symbol
Test
Conditions
SYSTEMINTERFACEPARAMETERS
Min. Max. Units
IDT72T7285
IDT72T7295
IDT72T72105
IDT72T72115
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
tTCKLOW
tTCKRISE
tTCKFALL
tRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
(1)
DataOutput
tDO
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tRSR
-
NOTE:
1. Guaranteed by design.
NOTE:
1. 50pf loading on external output signals.
28
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
