IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
BYTE ORDER ON INPUT PORT:
D71-D54
D71-D54
D53-D36
D53-D36
D35-D18
D17-D0
A
1st: Write to FIFO
2nd: Write to FIFO
B
D35-D18
D17-D0
C
D
BYTE ORDER ON OUTPUT PORT:
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM IW
OW
L
B
D
A
C
Read from FIFO
Read from FIFO
L
H
H
(a) x36 INPUT to x72 OUTPUT - BIG-ENDIAN
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM IW
OW
L
D
B
C
A
H
H
H
(b) x36 INPUT to x72 OUTPUT - LITTLE-ENDIAN
BYTE ORDER ON INPUT PORT:
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
A
1st: Write to FIFO
2nd: Write to FIFO
Q71-Q54
Q71-Q54
Q53-Q36
Q53-Q36
Q35-Q18
Q35-Q18
Q17-Q0
B
Q17-Q0
C
3rd: Write to FIFO
4th: Write to FIFO
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
D
BYTE ORDER ON OUTPUT PORT:
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM IW
OW
H
A
B
C
D
Read from FIFO
L
H
H
(a) x18 INPUT to x72 OUTPUT - BIG-ENDIAN
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM IW
OW
H
C
A
D
B
Read from FIFO
H
H
H
(b) x18 INPUT to x72 OUTPUT - LITTLE-ENDIAN
5994 drw10
Figure 5. Bus-Matching Byte Arrangement (Continued)
27
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
