IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
markedlocation.Duringretransmitmodewriteoperationstothedevicemay READ STROBE & READ CLOCK (RD/RCLK)
continuewithouthindrance.
IfSynchronousoperationofthereadporthasbeenselectedviaASYR,this
inputbehavesasRCLK.A readcycleisinitiatedontherisingedgeoftheRCLK
input. Datacanbereadontheoutputs,ontherisingedgeoftheRCLKinput.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dualpurpose pin. DuringMasterReset, the state ofthe FWFT/ ItispermissibletostoptheRCLK. NotethatwhileRCLKisidle,theEF/OR,PAE
SIinputdetermineswhetherthedevicewilloperateinIDTStandardmodeor andHFflagswillnotbeupdated.(NotethatRCLKisonlycapableofupdating
First Word Fall Through (FWFT) mode.
the HF flag to HIGH). The Write and Read Clocks can be independent or
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode coincident.
willbeselected. This modeuses theEmptyFlag(EF)toindicatewhetheror
If Asynchronous operation has been selected this input is RD (Read
notthereareanywordspresentintheFIFOmemory. ItalsousestheFullFlag Strobe) . Data is Asynchronouslyreadfromthe FIFOvia the outputregister
function(FF)toindicatewhetherornottheFIFOmemoryhasanyfreespace wheneverthereisarisingedgeonRD.InthismodetheRENandRCSinputs
forwriting. InIDTStandardmode,everywordreadfromtheFIFO,including mustbetiedLOW.TheOEinputisusedtoprovideAsynchronouscontrolofthe
the first, mustbe requestedusingthe ReadEnable (REN)andRCLK.
three-stateQnoutputs.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected. ThismodeusesOutputReady(OR)toindicatewhetherornotthere WRITE CHIP SELECT (WCS)
isvaliddataatthedataoutputs(Qn). ItalsousesInputReady(IR)toindicate
The WCS disables all Write Port inputs (data only) if it is held HIGH. To
whetherornottheFIFOmemoryhasanyfreespaceforwriting. IntheFWFT performnormaloperationsonthewriteport,theWCSmustbeenabled,held
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK LOW.
rising edges, REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (REN) and RCLK.
READ ENABLE (REN)
AfterMasterReset,FWFT/SIactsasaserialinputforloadingPAEandPAF
offsetsintotheprogrammableregisters. Theserialinputfunctioncanonlybe outputregisterontherisingedgeofeveryRCLKcycleifthedeviceisnotempty.
When Read Enable is LOW, data is loaded from the RAM array into the
usedwhentheserialloadingmethodhasbeenselectedduringMasterReset.
SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT andnonewdata is loadedintothe outputregister. The data outputs Q0-Qn
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdata
StandardandFWFTmodes.
maintainthepreviousdatavalue.
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
wordwrittentoanemptyFIFO, mustbe requestedusingREN providedthat
WRITE STROBE & WRITE CLOCK (WR/WCLK)
IfSynchronousoperationofthewriteporthasbeenselectedviaASYW,this RCSisLOW. WhenthelastwordhasbeenreadfromtheFIFO,theEmptyFlag
inputbehavesasWCLK.
(EF)willgoLOW,inhibitingfurtherreadoperations. RENisignoredwhenthe
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetup FIFOisempty.Onceawriteisperformed,EFwillgoHIGHallowingareadto
andholdtimesmustbemetwithrespecttotheLOW-to-HIGHtransitionofthe occur. TheEFflagisupdatedbytwoRCLKcycles+tSKEW afterthevalidWCLK
WCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,theFF/ cycle.BothRCSandRENmustbeactive,LOWfordatatobereadoutonthe
IR,PAFandHFflagswillnotbeupdated. (NotethatWCLKisonlycapableof rising edge of RCLK.
updating HF flag to LOW). The Write and Read Clocks can either be
independentorcoincident.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
totheoutputsQn,onthethirdvalidLOW-to-HIGHtransitionofRCLK+tSKEW
IfAsynchronousoperationhasbeenselectedthisinputisWR(writestrobe). afterthefirstwrite. RENandRCSdonotneedtobeassertedLOW fortheFirst
DataisAsynchronouslywrittenintotheFIFOviatheDninputswheneverthere Wordtofallthroughtotheoutputregister.Inordertoaccess allotherwords,
is arisingedgeonWR.Inthis modetheWENinputmustbetiedLOW.
a read must be executed using REN and RCS. The RCLK LOW-to-HIGH
transitionafterthelastword hasbeenreadfromtheFIFO,OutputReady(OR)
willgoHIGHwithatrueread(RCLKwithREN=LOW;RCS=LOW),inhibiting
further read operations. REN is ignored when the FIFO is empty.
IfAsynchronousoperationoftheReadporthasbeenselected,thenREN
mustbeheldactive,(tiedLOW).
WRITE ENABLE (WEN)
WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray
ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored
in the RAM array sequentially and independently of any ongoing read
operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles +tSKEW afterthe RCLKcycle.
SERIAL ENABLE ( SEN )
TheSENinput isanenableusedonlyforserialprogrammingoftheoffset
registers. The serialprogrammingmethodmustbe selectedduringMaster
Reset. SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
LOW-to-HIGHtransitionofSCLK.
Topreventdataoverflow intheFWFTmode, IR willgoHIGH,inhibiting
furtherwriteoperations. Uponthecompletionofavalidreadcycle,IRwillgo
LOWallowingawritetooccur. TheIRflagis updatedbytwoWCLKcycles +
tSKEW afterthe validRCLKcycle.
When SEN is HIGH, the programmable registers retains the previous
settingsandnooffsetsareloaded. SENfunctionsthesamewayinbothIDT
StandardandFWFTmodes.
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.
IfAsynchronousoperationofthewriteporthasbeenselected,thenWEN
mustbeheldactive,(tiedLOW).
OUTPUT ENABLE (OE )
WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive
datafromtheoutputregister. WhenOEisHIGH,theoutputdatabus(Qn)goes
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