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IDT72T7295L7BBI 参数 Datasheet PDF下载

IDT72T7295L7BBI图片预览
型号: IDT72T7295L7BBI
PDF下载: 下载PDF文件 查看货源
内容描述: 2.5 VOLT HIGH -SPEED TeraSyncTM FIFO 72位配置 [2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS]
分类和应用: 先进先出芯片
文件页数/大小: 53 页 / 536 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync  
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72  
                                                                                                                              
72-BIT FIFO  
                                                                                                                              
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
and read pointer when the MARK is asserted. (32 bytes = 16 word = 8 long  
words).Also,oncetheMARKisset,thewritepointerwillnotincrementpastthe  
“marked”locationuntiltheMARKisdeasserted.Thispreventsoverwriting”of  
retransmitdata.  
Onceamarkedlocationhasbeenset(andthedeviceisstillinretransmitmode,  
MARKisHIGH),aretransmitcanbeinitiatedbyarisingRCLKedgewhilethe  
retransmit input (RT) is LOW. REN must be HIGH (reads disabled) before  
bringingRTLOW.Thedeviceindicatesthestartofretransmitsetupbysetting  
OR HIGH.  
WhenOR goes LOW, retransmitsetupis complete andonthe nextrising  
RCLKedgeafterretransmitsetupiscomplete,(RTgoesHIGH),thecontents  
ofthefirstretransmitlocationareloadedontotheoutputregister.SinceFWFT  
modeisselected,thefirstwordappearsontheoutputsregardlessofREN,a  
LOWonRENisnotrequiredforthefirstword.Readingallsubsequentwords  
requires a LOW on REN to enable the rising RCLK edge. See Figure 19,  
RetransmitfromMarktiming(FWFTmode),fortherelevanttimingdiagram.  
Note,theremustbeaminimumof32bytesofdatabetweenthewritepointer  
HSTL/LVTTL I/O  
BoththewriteportandreadportareuserselectablebetweenHSTLorLVTTL  
I/O,viatwoselectpins,WHSTLandRHSTLrespectively.Allothercontrolpins  
are selectable via SHSTL, see Table 5 for details of groupings.  
Note,thatwhenthewriteportisselectedforHSTLmode,theusercanreduce  
thepowerconsumption(instand-bymodebyutilizingtheWCSinput).  
All “Static Pins” must be tied to VCC or GND. These pins are LVTTL only,  
andare purelydevice configurationpins.  
TABLE 5 — I/O CONFIGURATION  
WHSTL SELECT  
RHSTL SELECT  
SHSTL SELECT  
STATIC PINS  
WHSTL: HIGH = HSTL  
LOW = LVTTL  
RHSTL: HIGH = HSTL  
LOW = LVTTL  
SHSTL: HIGH = HSTL  
LOW = LVTTL  
LVTTL ONLY  
Dn (I/P)  
RCLK/RD (I/P)  
RCS (I/P)  
MARK (I/P)  
REN (I/P)  
OE (I/P)  
EF/OR (O/P)  
SCLK (I/P)  
LD (I/P)  
MRS (I/P)  
TCK (I/P)  
TMS (I/P)  
SEN (I/P)  
FWFT/SI (I/P)  
PRS (I/P)  
IW (I/P)  
BM (I/P)  
OW (I/P)  
ASYW (I/P)  
BE (I/P)  
FSEL0 (I/P)  
PFM (I/P)  
WHSTL (I/P)  
WCLK/WR (I/P)  
WEN (I/P)  
WCS (I/P)  
PAF (O/P)  
EREN (O/P)  
PAE (O/P)  
FF/IR (O/P)  
HF (O/P)  
TRST (I/P)  
TDI (I/P)  
ASYR (I/P)  
IP (I/P)  
FSEL1 (I/P)  
SHSTL (I/P)  
RHSTL (I/P)  
RT (I/P)  
Qn (O/P)  
ERCLK (O/P)  
TDO (O/P)  
20  
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