IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285
IDT72T7295
IDT72T72105
IDT72T72115
WCLK RCLK
SCLK
LD
WEN
REN
SEN
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
X
0
0
1
1
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
0
0
1
1
0
1
1
0
X
Full Offset (MSB)
Serial shift into registers:
X
X
28 bits for the IDT72T7285
30 bits for the IDT72T7295
32 bits for the IDT72T72105
34 bits for the IDT72T72115
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
X
X
X
1
1
1
No Operation
Write Memory
X
1
1
0
X
0
X
X
X
X
X
X
X
Read Memory
X
1
1
1
X
No Operation
5994 drw06
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 3. Programmable Flag Offset Programming Sequence
17
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
