IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Thecontentsoftheoffsetregisterscanbereadontheoutputlineswhenthe
A read and write should not be performed simultaneously to the offset
WriteEnable2/Load(WEN2/LD)pinissetLOWandbothReadEnables(REN1, registers.
REN2)aresetLOW. DatacanbereadontheLOW-to-HIGHtransitionofthe
Read Clock (RCLK).
IDT72421 - 64 x 9-BIT
IDT72201 - 256 x 9-BIT
8
8
8
8
6 5
0
0
0
0
8
8
8
8
7
0
0
0
0
Empty Offset (LSB) Reg.
Empty Offset (LSB) Reg.
Default Value 007H
Default Value 007H
6 5
7
Full Offset (LSB) Reg.
Default Value 007H
Full Offset (LSB) Reg.
Default Value 007H
IDT72211 - 512 x 9-BIT
IDT72221 - 1,024 x 9-BIT
8
8
8
7
0
0
0
8
7
0
0
0
0
Empty Offset (LSB) Reg.
Default Value 007H
Empty Offset (LSB)
Default Value 007H
1
1
8
8
8
(MSB)
(MSB)
00
0
7
7
Full Offset (LSB) Reg.
Default Value 007H
Full Offset (LSB)
Default Value 007H
8
1
0
1
(MSB)
00
(MSB)
0
IDT72231 - 2,048 x 9-BIT
IDT72241 - 4,096 x 9-BIT
IDT72251 8,192 x 9-BIT
8
8
8
8
7
0
8
8
8
8
7
0
0
0
0
8
8
8
8
7
0
0
0
0
Empty Offset (LSB) Reg.
Default Value 007H
Empty Offset (LSB)
Empty Offset (LSB)
Default Value 007H
Default Value 007H
2
0
0
0
3
4
(MSB)
(MSB)
(MSB)
000
0000
00000
7
7
7
Full Offset (LSB)
Full Offset (LSB)
Full Offset (LSB) Reg.
Default Value 007H
Default Value 007H
Default Value 007H
2
3
4
(MSB)
(MSB)
(MSB)
000
0000
00000
2655 drw 05
Figure 3. Offset Register Location and Default Values
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
