IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
NO WRITE
NO WRITE
NO WRITE
WCLK
tSKEW1
tDS
tSKEW1
D0 - D8
t
WFF
t
WFF
t
WFF
FF
(1)
(1)
t
ENH
tENS
t
ENS
WEN1
tENH
t
ENS
tENS
WEN2
(If Applicable)
RCLK
tENH
tENH
tENS
tENS
REN1,
REN2
tA
OE
LOW
tA
Q0
- Q8
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
2655 drw 10
NOTE:
1. Only one of the two write enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
Figure 8. Full Flag Timing
WCLK
tDS
tDS
D0 - D8
DATA WRITE 1
DATA WRITE 2
tENS
tENS
tENH
tENH
WEN1
tENS
tENS
tENH
tENH
WEN2
(If Applicable)
(1)
FRL
(1)
FFL
t
t
tSKEW1
tSKEW1
RCLK
tREF
tREF
tREF
EF
REN1,
REN2
OE LOW
tA
Q0
- Q8
DATA READ
DATA IN OUTPUT REGISTER
2655 drw 11
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK+ tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Figure 9. Empty Flag Timing
10
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
