ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 10 DC and AC Operating Conditions
ICS1892 Data Sheet
10.5.13 MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
Table 10-20 lists the significant time periods for the MII carrier assertion/de-assertion during half-duplex
transmission. The time periods consist of timings of signals on the following pins: TXEN, TXCLK, and CRS.
Figure 10-13 shows the timing diagram for the time periods.
Table 10-20. MII Carrier Assertion/De-Assertion (Half-Duplex Transmission Only)
Time
Parameter
Conditions Min. Typ. Max.
Units
Period
t1
t2
t3
TXEN Sampled Asserted to CRS Assert
TXEN Sampled De-Asserted to CRS De-Asserted
TXEN De-Asserted to CRS De-Asserted
–
–
–
–
–
–
< 1
< 1
–
1
1
4
Bit times
Figure 10-13. MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only)
t3
TXEN
TXCLK
CRS
t2
t1
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
