ICS1892
TSD
Chapter 10 DC and AC Operating Conditions
10Base-T/100BIaCseS-TX1I8nt9eg2rated PHYceiver™
10.5.16 Reset: Power-On Reset
Table 10-23 lists the significant time periods for the power-on reset (which consists of timings of signals on
the VDD and TXCLK pins). Figure 10-16 shows the timing diagram for the time periods.
Table 10-23. Power-On Reset Timing
Time
Period
Parameter
Conditions
Min.
Typ. Max. Units
200 ms
t1
VDD ≥ 4.75 V to Reset Complete
–
109
–
Figure 10-16. Power-On Reset Timing Diagram
4.75 V
VDD
t1
TXCLK
Valid
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
139
IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
139
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
