ICS1892
TSD
Chapter 10 DC and AC Operating Conditions
10Base-T/100BIaCseS-TX1I8nt9eg2rated PHYceiver™
10.5.10 10M Serial Interface: Transmit Latency
Table 10-17 lists the significant time periods for the 10M Serial Interface transmit latency. The time periods
consist of timings of signals on the following pins:
• 10TXEN (the 10M Serial Interface mapping of the 10M/100M MII TXEN pin)
• 10TCLK (the 10M Serial Interface mapping of the 10M/100M MII TXCLK pin)
• 10TD (the 10M Serial Interface mapping of the 10M/100M MII TXD0 pin)
• TP_TX (the MDI mapping of the 10M/100M MII TP_TXP and TP_TXN pins)
Figure 10-10 shows the timing diagram for the time periods.
Table 10-17. 10M Serial Interface Transmit Latency Timing
Time
Parameter
Conditions
Min. Typ. Max.
Units
Period
t1
10TD Into TP_TX Out Delay
10M Serial Interface
–
–
2
Bit times
Figure 10-10. 10M Serial Interface Transmit Latency Timing Diagram
10TXEN
10TCLK
10TD
Bit A
Bit B
(MDI)
TP_TX
Bit A
Bit B
t1
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
