ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 10 DC and AC Operating Conditions
ICS1892 Data Sheet
10.5.11 10M Media Independent Interface: Transmit Latency
Table 10-18 lists the significant time periods for the 10M MII transmit latency. The time periods consist of
timings of signals on the following pins: TXEN, TXCLK, TXD (that is, TXD[3:0]), and TP_TX (that is, the
TP_TXP and TP_TXN pins). Figure 10-11 shows the timing diagram for the time periods.
Table 10-18. 10M MII Transmit Latency Timing
Time
Period
Parameter
Conditions Min. Typ. Max.
10M MII 1.2
Units
t1
TXD Sampled to MDI Output of First Bit
–
2
Bit times
Figure 10-11. 10M MII Transmit Latency Timing Diagram
TXEN
TXCLK
TXD
5
5
5
TP_TX*
t1
*Manchester
encoding not
shown.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
134
IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
134
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
