ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 10 DC and AC Operating Conditions
ICS1892 Data Sheet
10.5.9 10M Media Independent Interface: Receive Latency
Table 10-16 lists the significant time periods for the 10M MII timing (which consists of timings of signals on
the following pins: TP_RX (that is, the MII TP_RXP and TP_RXN pins), RXCLK, and RXD. Figure 10-9
shows the timing diagram for the time periods.
Table 10-16.
Time
Period
Parameter
Conditions Min. Typ. Max.
10M MII 7.7
Units
t1
First Bit of /5/ on TP_RX to /5/D/ on RXD
–
9
Bit times
Figure 10-9. 10M MII Receive Latency Timing Diagram
TP_RX*
RXCLK
5
5
5
D
RXD
t1
*Manchester
encoding not
shown.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
