ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 10 DC and AC Operating Conditions
ICS1892 Data Sheet
10.5.17 Reset: Hardware Reset and Power-Down
Table 10-24 lists the significant time periods for the hardware reset and power-down reset (which consists
of timings of signals on the REF_IN, RESET*, and TXCLK pins). Figure 10-17 shows the timing diagram for
the time periods.
Table 10-24. Hardware Reset and Power-Down Timing
Time
Parameter
Conditions Min. Typ. Max. Units
Period
t1
RESET* Active to Device Isolation and
Initialization
–
–
65
–
ns
t2
t3
Minimum RESET* Pulse Width
–
–
200
–
–
–
ns
RESET* Released to TXCLK Valid
53
200
ms
Figure 10-17. Hardware Reset and Power-Down Timing Diagram
REF_IN
RESET*
t1
t2
t3
TXCLK
Valid
Power
Consumption
(AC only)
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
