ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 10 DC and AC Operating Conditions
ICS1892 Data Sheet
10.5.15 Media Dependent Interface: Input-to-Carrier Assertion/De-Assertion
Table 10-22 lists the significant time periods for the MDI input-to-carrier assertion/de-assertion. The time
periods consist of timings of signals on the following pins: CRS, COL, and TP_RX (that is, the TP_RXP and
TP_RXN pins). Figure 10-15 shows the timing diagram for the time periods.
Table 10-22. MDI Input-to-Carrier Assertion/De-Assertion Timing
Time
Period
Parameter
Conditions
Min.
9
Typ. Max.
Units
t1
t2
t3
t4
First Bit of /J/ into TP_RX to CRS
Assert †
–
–
–
–
–
13
13
17
14
Bit times
Bit times
Bit times
Bit times
First Bit of /J/ into TP_RX while
Transmitting Data to COL Assert †
Half-Duplex Mode
–
9
First Bit of /T/ into TP_RX to CRS
De-Assert ‡
13
–
First Bit of /T/ Received into TP_RX to Half-Duplex Mode
COL De-Assert ‡
† The IEEE maximum is 20 bit times.
‡ The IEEE minimum is 13 bit times, and the maximum is 24 bit times.
Figure 10-15. MDI Input to Carrier Assertion / De-Assertion Timing Diagram
First bit
First bit of /T/
TP_RX*
t3
t4
t1
CRS
COL
t2
*Shown
unscrambled.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
