ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 10 DC and AC Operating Conditions
ICS1892 Data Sheet
10.5.5 10M MII: Synchronous Transmit Timing
Table 10-12 lists the significant time periods for the 10M MII synchronous transmit timing (which consists of
timings of signals on the TXD[3:0], TXEN, TXER, and TXCLK pins). Figure 10-5 shows the timing diagram
for the time periods.
Table 10-12. 10M MII: Synchronous Transmit Timing
Time
Parameter
Conditions
Min.
Typ. Max. Units
Period
t1
t2
TXD[3:0], TXEN, TXER Setup to TXCLK Rise
TXD[3:0], TXEN, TXER Hold after TXCLK Rise
–
–
375
0
–
–
–
–
ns
ns
Figure 10-5. 10M MII Synchronous Transmit Timing Diagram
TXCLK
TXD[3:0]
TXEN
TXER
t1
t2
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
128
IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
128
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
