ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 10 DC and AC Operating Conditions
ICS1892 Data Sheet
10.5 Timing Diagrams
10.5.1 Timing for Clock Reference In (REF_IN) Pin
Table 10-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. Figure 10-1
shows the timing diagram for the time periods.
Note: The REF_IN switching point is 50% of VDD
.
Table 10-8. REF_IN Timing
Time
Parameter
Conditions
Min.
Typ. Max. Units
Period
t1
t2
REF_IN Duty Cycle
REF_IN Period
–
–
45
–
50
40
55
–
%
ns
Figure 10-1. REF_IN Timing Diagram
t1
REF_IN
t2
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
124
IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
124
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
