ICS1892
TSD
Chapter 10 DC and AC Operating Conditions
10Base-T/100BIaCseS-TX1I8nt9eg2rated PHYceiver™
10.5.8 10M Serial Interface: Receive Latency
Table 10-15 lists the significant time periods for the 10M Serial Interface timing (which consists of timings of
signals on the following pins:
• TP_RX (the MDI mapping of the 10M/100M MII TP_RXP and TP_RXN pins)
• 10RCLK (the 10M Serial Interface mapping of the 10M/100M MII RXCLK pin)
• 10RD (the 10M Serial Interface mapping of the 10M/100M MII RD0 pin)
Figure 10-8 shows the timing diagram for the time periods.
Table 10-15. 10M Serial Interface Receive Latency Timing
Time
Parameter
Conditions
Min. Typ. Max.
Units
Period
t1
TP_RX Input to 10RD Delay
10M Serial Interface
–
–
5
Bit times
Figure 10-8. 10M Serial Interface Receive Latency Timing
TP_RX
Bit A
Bit B
10RCLK
10RD
Bit A
Bit B
t1
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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