ICS1892
TSD
Chapter 10 DC and AC Operating Conditions
10Base-T/100BIaCseS-TX1I8nt9eg2rated PHYceiver™
10.5.2 Timing for Transmit Clock (TXCLK) Pin
Table 10-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pin for the various
interfaces. Figure 10-2 shows the timing diagram for the time periods.
Table 10-9. Transmit Clock Timing
Time
Parameter
Conditions
Min.
Typ. Max. Units
Period
t1
TXCLK Duty Cycle
TXCLK Period
TXCLK Period
TXCLK Period
TXCLK Period
–
35
–
50
40
65
–
%
ns
ns
ns
ns
t2a
t2b
t2c
t2d
100M MII (100Base-TX)
10M MII (10Base-T)
–
400
40
–
100M Symbol Interface (100Base-TX)
10M Symbol Interface (10Base-T)
–
–
–
100
–
Figure 10-2. Transmit Clock Timing Diagram
t1
TXCLK
t2x
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
