ICS1892
TSD
Chapter 10 DC and AC Operating Conditions
10Base-T/100BIaCseS-TX1I8nt9eg2rated PHYceiver™
10.5.4 100M MII / 100M Stream Interface: Synchronous Transmit Timing
Table 10-11 lists the significant time periods for the 100M MII / 100M Stream Interface synchronous
transmit timing (which consists of timings of signals on the TXD[3:0], TXEN, TXER, and TXCLK pins).
Figure 10-4 shows the timing diagram for the time periods.
Table 10-11. 100M MII / 100M Stream Interface: Synchronous Transmit Timing
Time
Parameter
Conditions
Min.
Typ. Max. Units
Period
t1
t2
TXD[3:0], TXEN, TXER Setup to TXCLK Rise
TXD[3:0], TXEN, TXER Hold after TXCLK Rise
–
–
15
0
–
–
–
–
ns
ns
Figure 10-4. 100M MII / 100M Stream Interface Synchronous Transmit Timing Diagram
TXCLK
TXD[3:0]
TXEN
TXER
t1
t2
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
