ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 10 DC and AC Operating Conditions
ICS1892 Data Sheet
10.5.3 Timing for Receive Clock (RXCLK) Pin
Table 10-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pin for the various
interfaces. Figure 10-3 shows the timing diagram for the time periods.
Table 10-10. MII Receive Clock Timing
Time
Parameter
Conditions
Min.
Typ. Max. Units
Period
t1
RXCLK Duty Cycle
RXCLK Period
RXCLK Period
RXCLK Period
RXCLK Period
–
35
–
50
40
65
–
%
ns
ns
ns
ns
t2a
t2b
t2c
t2d
100M MII (100Base-TX)
10M MII (10Base-T)
–
400
40
–
100M Symbol Interface (100Base-TX)
10M Symbol Interface (10Base-T)
–
–
–
100
–
Figure 10-3. Receive Clock Timing Diagram
t1
RXCLK
t2
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
126
IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
